Suppressing lithography at a wafer edge

ABSTRACT

Damage to the rim of a semiconductor wafer caused by etching processes is reduced by forming a rim of carbonized photoresist around the outer edge of the wafer, using a wafer edge tool to carbonize the outer rim of a positive tone photoresist.

BACKGROUND OF INVENTION

[0001] The field of the invention is that of lithography in integratedcircuit processing, in particular in patterning a wafer before an etchstep.

[0002] In the course of processing integrated circuits, a standardsequence is that of putting down a layer of material, then depositing alayer of photoresist, patterning the photoresist by projecting a patternon it and developing the resist to produce a pattern of open areas thatexpose the material, with the other areas still covered by the resist.

[0003] The etching process generates heat, so that it is preferred toextend the pattern to the edges of the wafer, even though the particularintegrated circuit at the edge will not fit on the wafer and thereforecannot be used. The reason for this is that performing the etching atthe edge tends to spread out the heat produced by the etching moreuniformly than if this were not done, thus reducing stress on the waferand the possibility of distortion.

[0004] A drawback of this approach is that, while it accomplishes itsprimary purpose of reducing stress, it sometimes permits or encouragesthe development of closely spaced sets of narrow cracks in the siliconwafer material, referred to as “Black” silicon, since it absorbs lightvery strongly. The narrow slivers of silicon between the cracks tend tobreak off, producing particles that cause defects in the integratedcircuit, and other problems.

[0005] Some etching tools have “shadow rings”, circular pieces of anetch-resistant material that blocks the etching process at the edge, asshown in FIG. 8 and discussed later. These tools have problems if theshadow ring contacts the wafer, which would contaminate the tool.Another drawback of using rings is that etching uniformity is degraded.In addition, the rings, being mechanical objects, are not positioned asprecisely as the lithographic patterns, requiring that space be left asa buffer between the ring position and the closest chip on the wafer.

[0006] The black silicon phenomenon is a problem only very close to theedge of a wafer, about 5 mm in current technology. It would be desirableto be able to block the etching in deep trench etching steps as requiredwith a controllable pattern that can be aligned with great precision.

SUMMARY OF INVENTION

[0007] The invention relates to a method of blocking etching in alocalized region of a wafer by damaging the resist used in patterningthe wafer.

[0008] A feature of the invention is blocking etching at the rim of thewafer.

[0009] A feature of the invention is the use of the same photoresistthat is used in the etching pattern.

[0010] Another feature of the invention is the use of an etch-resistantblocking layer.

[0011] Yet another feature of the invention is the removal of theblocking layer after a deep trench etching step.

BRIEF DESCRIPTION OF DRAWINGS

[0012]FIG. 1 shows a cross section of a wafer prepared for theinvention.

[0013]FIG. 2 shows the same area after exposure of the blocking layer.

[0014]FIG. 3 shows the area after development of the resist materialalso used for the blocking layer.

[0015]FIG. 4 shows the exposure of a wafer.

[0016]FIG. 5 shows a perspective view of apparatus for exposing a wafer.

[0017]FIG. 6A shows the area after processing according to the priorart.

[0018]FIG. 6B shows the area after processing according to theinvention.

[0019]FIG. 7 shows a top view of a wafer processed according to analternative embodiment of the invention.

[0020]FIG. 8 shows a cross section of a wafer being processed accordingto the prior art.

[0021]FIG. 9 shows a top view of a wafer that has been processedaccording to the invention.

DETAILED DESCRIPTION

[0022] The following describes an example of a process according to theinvention. A semiconductor wafer, e.g. Silicon, Gallium Arsenide,Silicon-Germanium alloy, Silicon on insulator, etc. is preparedaccording to the requirements of the circuit being fabricated and thetechnology in use.

[0023] A substrate or integrated circuit wafer 10 has a layer 11 on topthat represents schematically the pad nitride, pad oxide, and otherpreliminary layers, as shown in FIG. 1. The dimensions in the Figuresare not to scale. In the case of a three hundred millimeter diameterwafer, the relative proportion of the blocking material to be formed atthe rim to be defined, the thickness of the material and the diameter ofthe wafer will be as discussed below. The dimensions shown in thedrawing are selected for convenience in presentation and explanation.

[0024] A thick layer of positive photoresist 110 has been spun-on andprepared conventionally to be exposed and developed. In this case, it isa positive resist that is used to define deep trench patterns in DRAMsor embedded DRAM arrays. The pattern could be any pattern thatpotentially causes the problem of black silicon.

[0025] Next, as shown in FIG. 2, photoresist 110 is exposed at the rimover a radial distance 112 at the base of radiation beam 150 to define arim 115 that goes around the outer edge of wafer 10. The exposure ofbeam 150 will preferably be sufficient to carbonize the resist 110 overthat area. The distance 112 will preferably be uniform, but may be madenon-uniform, as discussed below.

[0026]FIG. 3 shows the result of exposing the central portion of thephotoresist with the regular pattern and then developing it, in whichthe central part of the photoresist has a deep trench pattern ofapertures 122 and the exposed part remains as a layer of blockingmaterial in a blocking area, defining a central inner area inside theblocking area for the construction of the integrated circuits.Repetition over the entire diameter of the wafer of the structures shownat the edges is indicated by the horizontal dotted line.

[0027] Layer 111 represents the pad nitride and also represents anoptional hardmask layer that can be etched through the openings in thephotoresist and will then define the etching operation in the underlyingsilicon. The pattern shown in resist 110 is referred to as the componentpattern. A hardmask is not always required and is used when the etchingprocess is more aggressive or lasts for a long time, so that photoresistalone is not enough to withstand the effects of the etching material.Bracket 114 represents a margin between blocking material 115 and theclosest part of a chip, to avoid damaging a chip by misalignment thatputs it on the material 115.

[0028] In FIG. 4, the same area is shown after the resist 110 has beenpatterned with the deep trench pattern and developed and the silicon inthe wafer 10 has been etched, forming trenches 124. Repetition over theentire diameter of the wafer of the structures etched in the wafer andshown at the edges is indicated by the horizontal dotted line. On bothsides, the rim 115 that has been carbonized by the edge exposure tool isseparated from the patterned and etched area by the buffer distance 114.

[0029] The thickness of layer 110 will be determined by the requirementsof the image being formed and the amount of etch resistance required.Since the photosensitive property of the photoresist has been destroyedby the process of carbonizing, the pattern does not develop in the rim.There is no remaining photoresist to protect the wafer from the etchinggases, as there is in the center. The carbonized resist remains and thatmaterial is more resistant to the etching than the original photoresist.The etching process is more aggressive at the wafer rim than it is ininterior locations, so that the etching gases may consume the carbonizedmaterial in places. It is an advantageous feature of the invention thatthe protection provided by the carbonized resist does not have to beperfect. The problem of black silicon does not arise when the etchinggases first attack silicon, but only after some material has beenattacked. Thus, the process according to the invention is tolerant offluctuations in blocking material thickness, etch resistance, etchingaggressiveness, etc.

[0030] The layer 115 will be stripped, e.g. in an oxygen plasma step,when no longer needed or when a chemical-mechanical polishing or otherplanarization step is to be performed that layer 115 would interferewith. If the layer has been completely consumed, then stripping is notrequired, but the operator cannot depend that it will be completelyconsumed.

[0031] In contemporary practice, the only etching process that suffersfrom the black silicon problem is deep trench etching, but new processesmay have a similar problem with a different step. New layers 115 may beformed as needed, though the deep trench represents the heaviest load onthe wafer, since it is the longest etching process.

[0032] The blocking layer can be applied in a single coating track,comprising the coating modules, hot plate modules, cool plate modules,developer units and a place for installing a wafer edge exposure module.A suitable tool that has been used for the invention is the ASML PAS5000scanner.

[0033] The invention is illustrated with a Wafer Edge Tool that has beendesigned to expose photoresist in the ultraviolet, (UV 196 nm-400 nm).Since the resist is to be carbonized, it may be preferred to use a lessexpensive laser in the infra-red or visible, so long as it can deliverenough power in the applied radiation dose to carbonize the resist 110.Electron beam tools may also be used, for example if the process isusing an electron beam tool to pattern the resist for the etching step.

[0034] The capability of dual-use (e.g. using the same wafer edge toolfor the conventional wafer edge exposure and also for the inventiveprocess) provides flexibility, but it may be that the use of a dedicatedtool has a lower capital cost.

[0035]FIG. 5 shows schematically the operation of a tool according tothe invention. Laser 510 generates a beam in the UV range that entersoptical fiber 540 that is positioned at the rim of wafer 10. The waferis rotated underneath fiber 540, so that radiation from the fiber, asbeam 150, strikes a strip at the rim of wafer 10. Mirrors 515 and 517are part of an alternative version of the invention that is discussedbelow.

[0036] In the ordinary use of the tool, shown in FIG. 6A, the radiationin beam 150 exposes the positive resist 110 in a strip about the rim, sothat the exposed resist, when developed, is removed from the rim,leaving a bare rim 115′ where the wafer is exposed. That reduces thepossibility of resist sticking to or otherwise contaminating other toolsthat come in contact with it.

[0037] According to the invention, the duration of the exposure and/orthe intensity of the radiation is set such that the radiation carbonizesor otherwise desensitizes the resist in that area. “Carbonize” is a termwell understood in the art that means that volatile compounds have beendriven out of the material, leaving a tough residue that is largelycarbon. Thus, when exposed according to the invention, the resist 110leaves a carbonized residue, shown as rim 115 in FIG. 6B, in the areathat usually is free from resist. When the resist in the central mainportion of the wafer is exposed with the pattern of deep trenches, therim is not developed, because the resist has been carbonized. Thus, thedesired result is achieved—that the deep trenches are not etched in thecarbonized rim.

[0038] The underlying silicon or other wafer material is protected fromthe etching gases by the carbonized residue and any optional hardmaskthat may be present. If a different etching process is used in someapplication that is not too aggressive and/or does not etch a thicklayer, it may be sufficient to cross-link, develop or otherwise renderthe resist in that area insensitive (e.g. a negative resist that becomesetch-resistant on exposure).

[0039] Referring now to FIG. 8, there is shown in cross section a priorart approach to protecting the wafer edge during etching. A mechanicalring 820, made of stainless steel or another material that willwithstand the etchant gases is positioned above the rim of wafer 10. Thering occupies a radial distance 112′ sufficient to protect the edge,which will vary in different tools and different chemistries. The ring820 is placed in position after the wafer is prepared with photoresist110 and remains in position during the etching step, so that the etchinggases do not attack the resist 110. The resist 110 underneath the ringhas been developed because the area at the edge of the wafer was exposedin order to improve the uniformity of heat loading during the etch.Thus, there are apertures in the photoresist at the wafer edge thatwould be attacked and etched if the ring were not present.

[0040]FIG. 9 shows a top view of a wafer exposed according to apreferred embodiment of the invention. There, it can be seen that therim 115 is a uniform piece of material that covers part of some chippatterns 922 at the edge of the wafer. Since the rim was exposed byrotating the wafer underneath the fiber carrying the carbonizingradiation, rim 115 has a smooth, circular edge.

[0041]FIG. 7 shows a corresponding top view of a wafer processedaccording to an alternative embodiment of the invention. Referring backto FIG. 5, an optional feature denoted generally by bracket 520 replacesthe optical fiber 540 for directing radiation on to the wafer. Twomirrors 515 and 517 are mounted to deflect the beam 150 in twoorthogonal directions, such as along x and y directions or along aradial direction and perpendicular to the radius. The radiation thentravels directly from the second mirror without passing through fiber540. Such an arrangement permits coverage of a broader exposure range onthe wafer than the diameter of fiber 540.

[0042] The wafer in FIG. 7 is divided in half with a dashed verticalline 750 in order to illustrate two embodiments of the invention. On theright, the tool that exposes material 110 does not have the capabilityof exposing an area having a 45 degree line (or other diagonal line) asan edge; i.e. it can only define vertical lines 708 and horizontal lines704. Accordingly, the blocking area 706 comes to the edge of the chips726. If desired, the area 706 could be defined to approach the waferedge up to a minimum distance 712 shown on the right side of the wafer,with a partial chip 726′ filling the gap between the nearest full chip726 and the blocking area, which would increase the area that ispatterned up to a maximum and approach the wafer edge more uniformlythan if partially exposed chip patterns were not used.

[0043] At the lower portion of the Figure, a line 714 is shown as analternative to a line 714′. The line 714′ would come too close to thewafer edge—i.e. the distance between the wafer edge and the closestchip, denoted as 712′, would be too small if a full chip were patternedalong line 714′. This location would have a more uniform heat load if apartial chip were used, similar to that shown on the right side of theFigure.

[0044] On the left side of the figure, the exposing tool is assumed tohave a 45 degree capability, so that diagonal lines 710 (at 45 degreesor at other angles) can be drawn. This capability permits a closerapproach to the wafer rim in various locations and can permit theexposure of a complete chip in some instances, and permit the moreuniform exposure of partial chips (and thus more uniform heat loading)in other cases. Such a partial chip 728 is indicated at the left side ofthe Figure.

[0045] Two different sizes of chips are shown for purposes ofillustration. Those skilled in the art will be aware that if the tool500 in FIG. 5 has precision position control, the length of individuallines can be made quite small and therefore coverage of the wafer canquite closely approximate a uniform ring of blocking material having theminimum distance 712. Such precision control is quite expensive, and itmay be that it is preferable to use a tool that has less precision andcan expose a pattern with much less precision, but is much lessexpensive. Precision placement takes time that decreases the throughputfor this exposure operation and thus increases the cost of practicingthe invention.

[0046] Since the effectiveness of resist 110 is destroyed bycarbonization, it does not matter if the resist is positive or negative.The blocking material 110 may be any positive tone photoresist ornegative tone photoresist.

[0047] An exposure tolerance for material 112 (i.e. a tolerablevariation in the inner radius of material 112, shown as bracket 114 inFIG. 3) is about 0.1 mm in contemporary technology. The primaryconsideration is not the precision of location, since this alignment isnon-critical, but the amount of area that cannot be printed with entirechips because of the need to allow for a margin of safety so that aproduction chip is not ruined by being projected on to the edge ofblocking material 112.

[0048] It is an advantageous feature of the invention, that the sameresist is used to define rim 115 and also to define the pattern in thecentral portion of the wafer. In the example illustrated, the resistused for the deep trench pattern is a positive resist, so a positiveresist is preferred to define rim 115. In some cases, it may benecessary to use a resist that does not have this dual capability, inwhich case, the central resist would be stripped and an appropriatesecond or pattern resist would be put down to receive the pattern ofthat layer of the circuit.

[0049] After the etching step, the integrated circuit fabricationprocess continues with conventional steps suitable for completing abipolar, CMOS, biCMOS, etc. integrated circuit; e.g. forming DRAM cells,forming planar transistors, one or more levels of the back endprocessing and packaging. Those skilled in the art will appreciate thatthe invention is not confined to DRAM processing or even to integratedcircuits (for example the invention may be used in micromachiningmechanical objects) and may be used with any etching process that has anadverse effect on the underlying layers of material on a region of thewafer. For example, though the etching process is more aggressive at therim, there could be processes where the need for the invention is foundin the interior of the wafer.

[0050] While the invention has been described in terms of a singlepreferred embodiment, those skilled in the art will recognize that theinvention can be practiced in various versions within the spirit andscope of the following claims.

1. A method of manufacturing a set of integrated circuits on a wafercomprising the steps of: preparing an integrated circuit substrate;depositing a layer of photosensitive material having a blockingthickness over said wafer; irradiating said photosensitive material in ablocking area at the outer edge of said wafer with a radiation dose suchthat said photosensitive material in said blocking area is desensitized;developing said photosensitive material to leave a layer of blockingmaterial in said area; exposing a layer of patterning photoresist insidesaid blocking area with a set of images of a component pattern of acomponent of said set of integrated circuits; etching said wafer throughsaid component pattern, while said blocking material blocks etching insaid blocking area; and continuing with processing said set ofintegrated circuits.
 2. A method according to claim 1, in which saidphotosensitive material is carbonized by said radiation dose.
 3. Amethod according to claim 1, in which said photosensitive material andsaid patterning photoresist are the same, so that said photosensitivematerial receives said set of images.
 4. A method according to claim 1,in which said images of said component pattern are images of deep trenchapertures in DRAM cells.
 5. A method according to claim 1, in which saidphotosensitive material is disposed over a layer of etch-resistantmaterial.
 6. A method according to claim 2, in which said photosensitivematerial is disposed over a layer of etch-resistant material.
 7. Amethod according to claim 3, in which said photosensitive material isdisposed over a layer of etch-resistant material.
 8. A method accordingto claim 1, in which said photosensitive material is positive tonephotoresist.
 9. A method according to claim 2, in which saidphotosensitive material is positive tone photoresist.
 10. A methodaccording to claim 3, in which said photosensitive material is positivetone photoresist.
 11. A method according to claim 1, in which saidradiation dose is delivered by rotating said wafer about its center, sothat said blocking area has an inner boundary comprising a circle.
 12. Amethod according to claim 1, in which said radiation dose is deliveredby deflecting said radiation along two orthogonal axes, so that saidblocking area has an inner boundary comprising a set of edges at rightangles.
 13. A method according to claim 2, in which said radiation doseis delivered by deflecting said radiation along two orthogonal axes, sothat said blocking area has an inner boundary comprising a set of edgesat right angles.
 14. A method of etching a set of apertures in aworkpiece comprising the steps of: depositing a layer of photosensitivematerial having a blocking thickness over said workpiece; desensitizingsaid photosensitive material in a blocking area at the outer edge ofsaid workpiece; exposing said layer of photosensitive material insidesaid blocking area with a set of images of said set of apertures;developing said photosensitive material to leave a layer of blockingmaterial in said blocking area and an aperture pattern outside saidblocking area; and etching said workpiece through said aperture pattern.15. A method according to claim 14, in which said images of said set ofapertures are images of deep trench apertures in DRAM cells.
 16. Amethod according to claim 14, in which said photosensitive material ispositive tone photoresist.
 17. A method according to claim 15, in whichsaid photosensitive material is positive tone photoresist.
 18. A methodaccording to claim 14, in which said blocking area has an inner boundarycomprising only edges at right angles.
 19. A semiconductor wafercomprising an inner area for the fabrication of integrated circuits andan outer rim resistant to etching and having a thickness such that anetching process does not etch in that area.
 20. A semiconductor waferaccording to claim 19, in which said rim is formed by carbonizing aphotoresist that is used to define a layer of an integrated circuit.